1. Field of the Invention
The present invention relates to storage circuits and, in particular, to storage circuits having a power-down-precharge mode.
2. Description of the Related Art
Many cases of use of storage circuits entail high demands on the energy consumption of said storage circuits, e.g. in the case of mobile phones, notebooks or other portable and self-contained devices of this type. Hence, most storage circuits, such as DDR-RAMs, SDRAM etc., have an energy-saving mode, e.g. the so-called power-down-precharge mode, in which all memory banks are inactive and most components of the storage circuit concerning the main functions of said storage circuit are switched off, said main functions being e.g. the reception, the processing and the output of read and write instructions and of the data and address signals associated therewith. For guaranteeing the minimum functions during the energy-saving mode, e.g. the discontinuance of said mode, it is also necessary to produce an internal clock signal from the external clock signal and, consequently, the clock receiver is on during the power-down-precharge mode. Due to the fact that said clock receiver is configured for high-speed applications, the current consumption is comparatively high.
It is the object of the present invention to provide a storage circuit and a method of operating the same so that the amount of energy consumed will be reduced.
The storage circuit according to the present invention comprises a first clock receiver circuit for receiving an external clock signal so as to produce from said external clock signal a first internal clock signal and so as to output the first internal clock signal for use within the storage circuit, and a second clock receiver circuit for receiving said external clock signal and for producing from said external clock signal a second internal clock signal, said second clock receiver circuit consuming less current than said first clock receiver circuit and having therefore a greater delay.
In addition, a circuit block is provided, which operates on the basis of said first or second internal clock signal and which is used for switching off said first clock receiver circuit when a power-down-precharge mode exists, said circuit block operating on the basis of said second internal clock signal, when the first clock receiver circuit has been switched off.
The invention starts from a storage circuit which comprises two clock receiver circuits of the above-mentioned type and in which, in the case of a self-refresh mode, i.e. a mode in which data are to be retained in the storage circuit and refreshed at regular intervals even if components external to the storage circuit are switched off and if no external clock signal is applied to the storage circuit, the first clock receiver circuit is switched off by a circuit block so that the circuit block, which operates on the basis of the first or of the second internal clock signal, will operate on the basis of the second internal clock signal, said circuit block operating, however, on the basis of the first internal clock signal from the first clock receiver circuit in the case of the power-down-precharge mode in this storage circuit.
The present invention is so conceived that the circuit block of the storage circuit operates on the basis of the second internal clock signal of the second clock receiver circuit also in the case of the power-down-precharge mode and switches off the first clock receiver circuit in said power-down-precharge mode. The power-down-precharge mode is an operating mode of the storage circuit in which essentially all the input buffers and the output buffers, with the exception of the two clock receivers, are deactivated. The power-down-precharge mode will be advantageous, i.e. it will save energy, especially in cases in which also the DLL is switched off, e.g. automatically upon entering the power-down-precharge mode, whereby even less current will be consumed. Up to now, this possibility has, however, not been practicable and advantageous in the final analysis, since the DLL needs a very large number of cycles, viz. approx. 200, for stabilizing. More modern DLLs recover, however, in a few, e.g. two, cycles so that, on the whole, a deactivation of the faster clock receiver is advantageous also in the power-down-precharge mode.
The present invention is based on the finding that in the power-down-precharge mode a reduced current consumption can be achieved by using, instead of the faster clock receiver circuit, i.e. the clock receiver circuit which has a shorter delay and which, due to the high speed requirements, is normally used in the other operating modes, such as reading or writing, a slower clock receiver circuit for producing the internal clock signal from the external clock signal; also said slower clock receiver circuit produces a further internal clock signal from the external clock signal, but it consumes less current and has therefore a greater delay than the first clock receiver circuit. The greater delay caused by the slower clock receiver circuit is acceptable in the power-down-precharge mode, since read and write processes are not carried out in this mode anyhow.
Preferred further developments of the present invention are the subject matter of the subclaims.